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PRODUCTS & SOLUTIONS - CIRCUIT SIMULATION & DESIGN FOR YIELD SOLUTIONS
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High Yield Analysis Technology - HighSigmaPro (HSP)
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For repetitive structure circuits like memory, in which an extremely low cell failure rate (high σ) is necessary to ensure high
chip yield, the traditional Monte Carlo is practically impossible to finish needed sampling, as it usually requires millions,
even billions of runs. The validated HighSigmaPro technology is developed based on IBM-licensed patents, and can cut
Monte Carlo sampling by orders of magnitude. Taking a 1Mb SRAM as an example, the yield of a bitline cell needs to reach
as high as 99.999999% ( Pf < 1e-8, i.e., 5-6σ) in order to achieve the SRAM chip yield to be 99% (Pf < 0.01). Comparing to the
billions of samples required by traditional Monte Carlo, the HSP technology only needs thousands of samples to achieve
the same accuracy, which significantly shortens statistical simulation time and makes it possible for designers to do yield
analysis for this kind of applications.
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(The above results are run based on a 4-core system)
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Features
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Based on the NanoSpice™ parallel statistical SPICE engine and NanoYield™ DFY toolset
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HSP technology delivers significant speed-up over traditional Monte Carlo,
and can accurately predict an extremely low failure rate of cell blocks, for
example, 5-6σ
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Validated for memory, sensitive digital/ASIC circuits (decoder circuit library,
hit logic, dynamic latch library, clock buffers, standard cells), etc.
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Rich analysis functions, including sensitivity analysis, dependence analysis,
High Sigma analysis, etc., and can be used for early yield predictions and
design optimizations
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Application Examples
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SRAM uses the most aggressive design rules, i.e., the smallest and
densest devices to achieve the highest density; however the unavoid-able
process variations between neighboring devices will degrade circuit
performance and lead to cell failure
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The process variations at advanced technologies become more severe,
leading to larger impact to SRAM yield
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NanoYield™ can easily predict SRAM yield at a given process (variation)
information, and therefore can be used in early process evaluation for
technology development and DFY-oriented design optimization of
circuit designs
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* HSP technology accurately predicted SRAM yield on a 65nm technology (IBM, 2011)
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